Σχολή Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών

Μόνιμο URI για αυτήν την κοινότηταhttps://dspace.library.tuc.gr/handle/123456789/2

Μέχρι και τον Ιούνιο του 2016, η Σχολή Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών ονομαζόταν Σχολή Ηλεκτρονικών Μηχανικών και Μηχανικών Υπολογιστών.

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Implementation and evaluation of dynamic partial reconfiguration techniques on cryptographic algorithms
(Πολυτεχνείο Κρήτης, 2014) Kasabalis Vasileios; Κασαμπαλης Βασιλειος; Pnevmatikatos Dionysios; Πνευματικατος Διονυσιος; Dollas Apostolos; Δολλας Αποστολος; Koutroulis Eftychios; Κουτρουλης Ευτυχιος
In recent years the advantages of reconfigurable computing have make FPGAs important parts of many applications. One interesting characteristic of FPGAs is their ability to change parts of the design that runs on them dynamically. This procedure is called Partial Reconfiguration (PR). One disadvantage of PR is that sometimes it takes too much time to be completed and for real-time applications it has to be able to be executed fast. The purpose of this thesis is the implementation of designs that can perform PR with high throughput. When a reconfiguration is taken place a partial bitstream file must be transferred from a memory where it is stored to the reconfiguration memory of the FPGA. This transfer can be executed by software code that runs on a processor (e.g. PowerPC or MicroBlaze) or by hardware. For this thesis several designs were implemented, each one uses one of these methods to transfer the partial bitstream and a deferent memory where the partial bitstreams are stored. The memories that were used on these designs were a Compact Flash, a DDR2 SDRAM and a SRAM. The final result was a design that can perform PR with high throughput.
Run time system implementation for concurrent H/W S/W task execution on FPGA platforms
(Technical University of Crete, 2015) Koidis Iosif; Κοϊδης Ιωσηφ; Pnevmatikatos Dionysios; Πνευματικατος Διονυσιος; Dollas Apostolos; Δολλας Αποστολος; Samoladas Vasilis; Σαμολαδας Βασιλης
In the recent years, technology have made possible to fit a larger number of components on a single chip, and allowed us to realize larger, more complex chips. The large transistor budget can be used to create heterogeneous systems, generally called Multiprocessor Systems-on-Chip (MPSoC). It also allowed the creation of larger FPGA devices, integrating ample amounts of programmable logic, memories, programmable DSP/arithmetic units. Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the functionality of computing systems, swapping in and out HW tasks. In this thesis we describe the integration process of a Run Time System Manager (RTSM) able to map multiple applications on the underlying architecture, which may consist of microprocessors as software processing elements and Partially Reconfigurable areas as hardware processing elements, and execute them concurrently. In this thesis we describe the integration process of a Run Time System Manager (RTSM) able to map multiple applications on the underlying architecture and execute them concurrently. The RTSM is able to schedule application tasks either on available processor core(s), or at the FPGA hardware resources using partial reconfiguration. The choice is made dynamically based on availability and a gain function VERIFY. We integrate and the RTSM on two different system architectures and corresponding platforms in order to demonstrate the RTSM portability and a real time application is used in order to validate its correctness and potential. The two aforementioned embedded platforms are the Xilinx XUPV5 board which hosts a Virtex 5 LX 110T device and the Zedboard platform which hosts a • Zynq®-7000 All Programmable SoC XC7Z020-CLG484-1.

Περιηγούμαι

Πλοήγηση Σχολή Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών ανά Θέμα "adaptive computing"