Run time system implementation for concurrent H/W S/W task execution on FPGA platforms

Abstract

In the recent years, technology have made possible to fit a larger number of components on a single chip, and allowed us to realize larger, more complex chips. The large transistor budget can be used to create heterogeneous systems, generally called Multiprocessor Systems-on-Chip (MPSoC). It also allowed the creation of larger FPGA devices, integrating ample amounts of programmable logic, memories, programmable DSP/arithmetic units. Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the functionality of computing systems, swapping in and out HW tasks. In this thesis we describe the integration process of a Run Time System Manager (RTSM) able to map multiple applications on the underlying architecture, which may consist of microprocessors as software processing elements and Partially Reconfigurable areas as hardware processing elements, and execute them concurrently. In this thesis we describe the integration process of a Run Time System Manager (RTSM) able to map multiple applications on the underlying architecture and execute them concurrently. The RTSM is able to schedule application tasks either on available processor core(s), or at the FPGA hardware resources using partial reconfiguration. The choice is made dynamically based on availability and a gain function VERIFY. We integrate and the RTSM on two different system architectures and corresponding platforms in order to demonstrate the RTSM portability and a real time application is used in order to validate its correctness and potential. The two aforementioned embedded platforms are the Xilinx XUPV5 board which hosts a Virtex 5 LX 110T device and the Zedboard platform which hosts a • Zynq®-7000 All Programmable SoC XC7Z020-CLG484-1.