Reliable runtime architecture for multiprocessor systems on chip

dc.contributorΠρατικάκης Πολύβιοςel
dc.contributorPratikakis Polyviosen
dc.contributor.advisorPnevmatikatos Dionysiosen
dc.contributor.advisorΠνευματικατος Διονυσιοςel
dc.contributor.authorSkarlatos Dimitriosen
dc.contributor.authorΣκαρλατος Δημητριοςel
dc.contributor.committeememberDollas Apostolosen
dc.contributor.committeememberΔολλας Αποστολοςel
dc.contributor.committeememberPapaefstathiou Ioannisen
dc.contributor.committeememberΠαπαευσταθιου Ιωαννηςel
dc.date.accessioned2024-10-31T15:16:19Z
dc.date.available2024-10-31T15:16:19Z
dc.date.issued2014
dc.date.submitted2014-06-03
dc.descriptionΠροπτυχιακή Διατριβή που υποβλήθηκε στη σχολή ΗΜΜΥ του Πολ. Κρήτης για την πλήρωση προϋποθέσεων λήψης του Προπτυχιακού Διπλώματος Ειδίκευσης.el
dc.description.abstractMission critical applications rely on both hardware- and software-approaches for fault-tolerance. With the adoption of multiprocessor systems on chip (MPSoCs), processor fault-tolerance with modular redundancy has become a major issue, cost and performance wise. In this thesis first , we augment a task-parallel runtime system with support for transparent checkpoints of task data that may be written during task execution and seamlessly rerun failed tasks. The system can recover from transient errors during task execution within a single core by rerunning the failed task, as well as from permanent errors that disable a worker core by redistributing work among remaining cores. We have evaluated our implementation using six benchmarks and found that checkpointing incurs a performance overhead of 8\% on average, mainly due to the cost of memory copies, and only a negligible space overhead due to the recycling of checkpoint memory. Then, in order to protect the workers runtime system beyond the execution stage, we present ASGUARDIAN, a lightweight hardware mechanism based on a task-oriented model for general programmability. The ASGUARDIAN features both store-and-forward and cut-through capabilities to reliably transfer task descriptions and arguments between main memory and available worker cores. It also isolates the workers from accessing the main memory. A hardware prototype has been implemented on a Xilinx ML605 FPGA board using the widely-used ARM AMBA protocol. Introducing the ASGUARDIAN reliability features results in a 8% average overhead on hardware resources for a configuration with four Microblaze cores. The performance overhead for the store-and-forward and cut-through implementations were 2.3x and 1.2x respectively against an unprotected, shared memory system. When compared against an -unprotected- scratchpad-based memory system, the store-and-forward version showed an overhead of 1.7x, while the cut-through version showed a speedup of 6% on average.en
dc.format.extent60 pagesen
dc.identifier10.26233/heallink.tuc.17741
dc.identifier.citationDimitrios Skarlatos, "Reliable runtime architecture for multiprocessor systems on chip", Diploma Work, School of Electronic Engineering, Technical University of Crete, Chania, Greece, 2014el
dc.identifier.citationΔημήτριος Σκαρλάτος, "Reliable runtime architecture for multiprocessor systems on chip", Διπλωματική Εργασία, Σχολή Ηλεκτρονικών Μηχανικών και Μηχανικών Υπολογιστών, Πολυτεχνείο Κρήτης, Χανιά, Ελλάς, 2014el
dc.identifier.urihttps://dspace.library.tuc.gr/handle/123456789/428
dc.language.isoen
dc.publisherΠολυτεχνείο Κρήτηςel
dc.publisherTechnical University of Creteel
dc.relation.replaces5292
dc.rightshttp://creativecommons.org/licenses/by/4.0/en
dc.subjectComputing, Fault-toleranten
dc.subjectfault tolerant computingen
dc.subjectcomputing fault toleranten
dc.subjectComputer reliabilityen
dc.subjectcomputers reliabilityen
dc.subjectcomputer reliabilityen
dc.subjectCLR (Common Language Runtime)en
dc.subjectcommon language runtime computer scienceen
dc.subjectclr common language runtimeen
dc.subjectSOC designen
dc.subjectSystems on chipen
dc.subjectsystems on a chipen
dc.subjectsoc designen
dc.subjectsystems on chipen
dc.subjectMulticoresen
dc.subjectTask Based Programming Modelen
dc.subjectField programmable logic arraysen
dc.subjectFPGAsen
dc.subjectfield programmable gate arraysen
dc.subjectfield programmable logic arraysen
dc.subjectfpgasen
dc.titleReliable runtime architecture for multiprocessor systems on chipen
dc.typeΔιπλωματική Εργασίαel
dc.typeDiploma Worken
dcterms.mediatorΠολυτεχνείο Κρήτης::Σχολή Ηλεκτρονικών Μηχανικών και Μηχανικών Υπολογιστώνel
dspace.entity.typePublication

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